1. Field of the Invention
The invention relates in general to a structure of a package on package and a method for fabricating the same, and more particularly to a structure of a package on package connected by pins and a method for fabricating the same.
2. Description of the Related Art
As portable multimedia devices become more and more popular, the trend toward new storage structures with higher digital signal processing, larger storage capacity and more flexibility grows accordingly. Therefore, the application of stacked package on package (PoP) extends rapidly.
The package on package is a new three-dimensional packaging technology with lowest cost for logic and memory Integration. The stacked package on package is used for developing devices with new appearance or higher integration. Also, the package on package has small volume due to stacked structure. Therefore, the size of the mother board is not increased or even reduced.
FIG. 1 is a cross-sectional view of a conventional package on package. Please referring to FIG. 1, the structure of the conventional package on package 10 includes an upper package 12 and a lower package 14 connected together by solder balls 20. A chip 18, circuits and the solder balls 20 are disposed on a surface of a substrate 16 of the lower package 14.
The available space for disposing the circuits is limited because the solder balls 20 and the circuits are both disposed on the lower substrate 16. Therefore, it is difficult to dispose vias when the circuits have to be disposed on inner layers. It is even more difficult to disposes the circuits in the high-density area adjacent to the chip 18. Therefore, multilayer technology is used or the size of the package is increased for solving the above problems.